Xilinx 1000BASE-X Manuel d'utilisateur télécharger pdf (Page 208)

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UG155 March 24, 2008

Appendix B: Core Latency

Latency for 1000BASE-X PCS and PMA Using a RocketIO Transceiver

These measurements are for the core only–they do not include the latency through the

Virtex-II Pro or Virtex-4 MGT, Virtex-5 GTP transceiver, or the Transmitter Elastic Buffer

added in the example design.

Transmit Path Latency

As measured from a data octet input into gmii_txd[7:0] of the transmitter side GMII

(until that data appears on txdata[7:0] on the MGT interface), the latency through the

core in the transmit direction is 4 clock periods of userclk2.

Receive Path Latency

As measured from a data octet input into the core on rxdata[7:0] from the MGT

interface (until that data appears on gmii_rxd[7:0] of the receiver side GMII), the

latency through the core in the receive direction is 6 clock periods of userclk2.

Latency for SGMII

When performing the SGMII standard, the core latency figures are identical to the Latency

for 1000BASE-X PCS and PMA using the MGT. Again these figures do not include the

latency through the MGT or any Elastic Buffers added in the example design.

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Xilinx 1000BASE-X Manuel d'utilisateur Page 208