Xilinx UG492 manuels

Xilinx UG492 Manuel d'utilisateur (172 pages)

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Table des matières

LogiCORE

1

Ethernet AVB

1

Endpoint v2.4

1

Revision History

2

Table of Contents

3

Chapter 5: Core Architecture

4

Schedule of Figures

9

UG492 July 23, 2010

10

Schedule of Tables

13

Chapter 13: Software Drivers

14

About This Guide

17

Conventions

18

Online Document

19

List of Abbreviations

20

Preface: About This Guide

22

Recommended Design Experience

24

Additional Core Resources

24

Technical Support

24

Feedback

24

Document

25

Chapter 1: Introduction

26

Licensing the Core

27

Obtaining Your License Key

28

Installing the License File

28

Bridging

29

AVB Specifications

30

P802.1Qav

31

Typical Implementation

32

Component Name

36

Core Delivery Format

36

Ethernet AVB GUI Page 2

37

Output Generation

38

Core Architecture

39

EDK pcore Format

41

Functional Block Description

42

Tx Arbiter

43

Rx Splitter

43

MAC Header Filters

43

Tx PTP Packet Buffers

44

Tx Time Stamp

44

Rx PTP Packet Buffers

44

Rx Time Stamp

44

Tri-Mode Ethernet MACs

46

Core Interfaces

47

Legacy Traffic Interface

48

AV Traffic Interface

49

MAC Transmitter Interface

50

MAC Receiver Interface

51

MAC Management Interface

51

PLB Interface

53

Chapter 5: Core Architecture

54

Interrupt Signals

55

PTP Signals

56

Chapter 6

57

Tx AV Traffic I/F

59

Tx Arbiter Bandwidth Control

63

Chapter 7

65

Legacy MAC Header Filters

67

Match Pattern Register

70

Match Enable Register

70

VLAN Priority Match

72

Any Other Combinations

72

Rx AV Traffic I/F

73

Errored AV Traffic Reception

74

Chapter 8

75

RTC Implementation

77

(Step 2) Synchronized RTC

78

Time Stamping Logic

79

Chapter 9

83

Rx PTP Packet Buffer

85

Configuration and Status

87

Single Write Transaction

89

Rx Filtering Control Register

93

TC nanoseconds field. Used

94

Current RTC Value Registers

95

RTC Interrupt Clear Register

96

Phase Adjustment Register

97

MAC Address Filter Registers

100

MAC MDIO Registers

101

Constraining the Core

103

signal:

104

Required Constraints

107

"rtc_regs_sample";

109

System Integration

111

Introduction

124

EDK Tool Domain

125

Ethernet

125

MHS File Syntax

127

Software Drivers

131

Clock Slave

132

Software System Integration

132

Core Initialization

134

Ethernet AVB Endpoint Setup

134

Quick Start Example Design

137

Generating the Core

139

Simulating the Example Design

141

What’s Next?

142

Chapter 15

143

Directory and File Contents

144

<component name>/doc

145

Table 15-9: Timing Directory

148

Implementation Scripts

151

Simulation Scripts

151

Example Design

152

Top-Level Example Design HDL

153

Ethernet Frame Stimulus

153

Ethernet Frame Checker

154

Loopback Module

154

PLB Module

155

Demonstration Test Bench

156

Customizing the Test Bench

157

X-Ref Target - Figure 15-3C

158

Development Kit (EDK)

165

RTC Time Stamp Accuracy

167

0 40 80 120 160 200 240RTC

168

RTC Sampling Error

169

Sampling

170

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