Xilinx 8.2i manuels

Xilinx 8.2i Manuel d'utilisateur (148 pages)

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Table des matières

MicroBlaze

1

Processor

1

Reference Guide

1

1-800-255-7778

2

UG081 (v6.0) June 1, 2006

3

About This Guide

7

Conventions

8

Online Document

9

Preface: About This Guide

10

MicroBlaze Architecture

11

Data Types and Endianness

13

Instructions

13

Registers

20

General Purpose Registers

21

Special Purpose Registers

21

Machine Status Register (MSR)

22

Arithmetic Carry

24

Interrupt Enable

24

Buslock Enable

24

19 20 26 27 31

25

RESERVED

25

Branch Target Register (BTR)

26

Invalid operation

27

Divide-by-zero

27

Underﬂow

27

Denormalized operand error

27

Pipeline Architecture

31

Memory Architecture

32

← 0x00000000

34

Equivalent Pseudocode

35

Hardware Breaks

35

Interrupt

36

User Vector (Exception)

36

← 0x00000008

37

Instruction Address Bits

37

Data Cache

38

Data Address Bits

39

Floating Point Unit (FPU)

40

Rounding

41

Operations

41

Fast Simplex Link (FSL)

42

Debug and Trace

43

Chapter 2

45

LMB Signal Interface

49

LMB Transactions

51

Back-to-Back Write Operation

52

Read and Write Data Steering

53

Master FSL Signal Interface

54

Slave FSL Signal Interface

54

FSL Transactions

55

CacheLink Signal Interface

56

CacheLink Transactions

57

Instruction Cache Read Miss

58

Data Cache Read Miss

58

Data Cache Write

58

Debug Interface Description

59

Trace Interface Description

59

MicroBlaze Application Binary

65

Interface

65

Register Usage Conventions

66

Stack Convention

67

Memory Model

69

≠ Not equal comparison

71

Logical AND

75

(rD) ← (rA) ∧ (rB)

75

Logial AND with Immediate

76

← (rA) ∧ sext(IMM)

76

Logical AND NOT

77

← (rA) ∧ (rB)

77

← (rA) ∧ (sext(IMM))

78

Branch if Equal

79

← PC + rB

79

← PC + 4

79

Branch Immediate if Equal

80

← PC + sext(IMM)

80

Branch if Greater or Equal

81

Branch if Greater Than

83

Branch if Less or Equal

85

Branch if Less Than

87

Branch Immediate if Less Than

88

Branch if Not Equal

89

≠ 0 then

89

Branch Immediate if Not Equal

90

Unconditional Branch

91

← PC + (rB)

91

← PC + (IMM)

93

Break Immediate

96

← sext(IMM)

96

Floating Point Arithmetic Add

100

Description

101

Pseudocode

101

Registers Altered

101

Immediate

108

Load Byte Unsigned

109

←(rA) + (rB)

109

← Mem(Addr)

109

Load Byte Unsigned Immediate

110

←(rA) + sext(IMM)

110

Load Word

113

← (rA) + (rB)

113

Load Word Immediate

114

← (rA) + sext(IMM)

114

← (MSR) ∧ (IMM))

116

Read MSR and set bits in MSR

117

← (MSR) ∨ (IMM)

117

Multiply

119

← LSW( (rA) × (rB) )

119

Multiply Immediate

120

← LSW( (rA) × sext(IMM) )

120

Logical OR

121

← (rA) ∨ (rB)

121

Logical OR with Immediate

122

← (rA) ∨ (IMM)

122

Pattern Compare Equal

124

Pattern Compare Not Equal

125

Return from Break

129

Return from Interrupt

130

Return from Subroutine

132

Store Byte

133

← (rD)[24:31]

133

Store Byte Immediate

134

Sign Extend Halfword

135

← (rA)[16]

135

← (rA)[16:31]

135

Sign Extend Byte

136

← (rA)[24]

136

← (rA)[24:31]

136

Store Halfword

137

← (rD)[16:31]

137

Store Halfword Immediate

138

Shift Right Arithmetic

139

← (rA)[0]

139

← (rA)[0:30]

139

← (rA)[31]

139

Shift Right with Carry

140

← MSR[C]

140

Shift Right Logical

141

Store Word

142

← (rD)[0:31]

142

Store Word Immediate

143

Write to Data Cache

144

Write to Instruction Cache

145

Logical Exclusive OR

146

← (rA) ⊕ (rB)

146

← (rA) ⊕ sext(IMM)

147

UG018 Manuel d'utilisateur Anglais

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