Xilinx V3.0 Manuel d'utilisateur Page 27
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PCI v3.0.151 Getting Started Guide www.xilinx.com 27
UG157 August 31, 2005
Design Support
R
See the product release notes included with the core for a complete directory structure and
file list.
4VSX35-FF668-11C/I
regional clock
66 MHz
3.3V
32-bit
pcim_lc_66_3r 4vsx35ff668_32_33r.ucf
no guide file
4VFX20-FF672-11C/I
regional clock
66 MHz
3.3V
32-bit
pcim_lc_66_3r 4vfx20ff672_32_33r.ucf
no guide file
Table 3-1: Device and Interface Selection Table (Continued)
Supported
Device
Bus
Type
Wrapper File
Constraints File/
Guide File
- LogiCORE™ 1
- PCI v3.0 1
- Table of Contents 5
- Chapter 7: Timing Simulation 6
- About This Guide 7
- Additional Resources 8
- Conventions 8
- Online Document 9
- Preface: About This Guide 10
- Getting Started 11
- Technical Support 12
- Feedback 12
- Chapter 2 13
- UG157 August 31, 2005 14
- Licensing Options 16
- Installing Your License File 17
- Chapter 3 19
- Wrapper Files 28
- Constraints Files 28
- Guide Files 28
- Device Initialization 29
- Bus Width Detection 29
- Datapath Output Clock Enable 30
- Input Delay Buffers 30
- Regional Clock Usage 32
- Bus Clock Usage 34
- Electrical Compliance 35
- VCCINT (V) 36
- System Supply (V) 36
- 3.3V PCI COMPLIANT 36
- Generating Bitstreams 37
- Functional Simulation 39
- Model Technology ModelSim 40
- Synthesizing a Design 43
- Exemplar LeonardoSpectrum 51
- Xilinx XST 52
- Implementing a Design 53
- Timing Simulation 55
- Chapter 7: Timing Simulation 58
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