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1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com 15
UG144 April 24, 2009
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Preface
About This Guide
The LogiCORE™ IP 1-Gigabit Ethernet MAC User Guide provides information about
generating the core, customizing and simulating the core utilizing the provided example
design, and running the design files through implementation using the Xilinx tools.
Guide Contents
This guide contains the following chapters:
• Preface, “About this Guide” introduces the organization and purpose of the guide
and the conventions used in this document.
• Chapter 1, “Introduction” describes the core and related information, including
recommended design experience, additional resources, technical support, and
submitting feedback to Xilinx.
• Chapter 2, “Core Architecture” provides an overview of the core and discusses the
Physical/Client signal interfaces.
• Chapter 3, “Generating the Core” describes the graphical user interface options used
to generate the core.
• Chapter 4, “Designing with the Core” through Chapter 8, “Configuration and Status”
describe design parameters, including how to initialize the core, generate and
consume core packets, and how to operate the Management Interface.
• Chapter 9, “Constraining the Core” describes the constraints associated with the core.
• Chapter 10, “Clocking and Resetting” discusses special design considerations
associated with clock management logic, including the Gigabit Media Independent
Interface (GMII) and Reduced Gigabit Media Independent Interface (RGMII) options.
• Chapter 11, “Interfacing to Other Cores” describes how to interface the 1-Gigabit
Ethernet MAC core to the Ethernet 1000BASE-X PCS/PMA or SGMII core and the
Ethernet Statistics core.
• Chapter 12, “Implementing Your Design” provides instructions for how to set up
synthesis, simulation, and implementation environments and how to generate a
bitstream through the design flow.
• Appendix A, “Using the Client-Side FIFO” describes the FIFO provided in the
example design that accompanies the GEMAC core.
• Appendix B, “Core Verification, Compliance, and Interoperability” describes how the
core was verified and certified for compliance.
• Appendix C, “Calculating DCM Phase-Shifting” provides information about how to
calculate the system timing requirements when using DCMs with the core.
• Appendix D, “Core Latency” describes the latency of the core.
- LogiCORE™ IP 1
- 1-Gigabit Ethernet 1
- MAC v8.5 1
- Revision History 3
- Table of Contents 5
- Appendix D: Core Latency 8
- Schedule of Figures 9
- UG144 April 24, 2009 10
- Schedule of Tables 13
- About This Guide 15
- Conventions 16
- Online Document 17
- List of Acronyms 17
- Introduction 19
- Specifications 20
- Technical Support 20
- Feedback 20
- Core Architecture 21
- Core Components 22
- Core Interfaces 23
- Client Side Interface 26
- Receiver Interface 27
- Flow Control Interface 27
- Physical Side Interface 29
- MDIO Interface 30
- Generating the Core 31
- Component Name 32
- Management Interface 32
- Address Filter 32
- Physical Interface 32
- Output Generation 33
- Designing with the Core 35
- Know the Degree of Difficulty 37
- Keep it Registered 38
- Use Supported Design Flows 38
- Chapter 5 39
- Frame Reception with Errors 41
- Client-Supplied FCS Passing 42
- VLAN Tagged Frames 42
- Disabled 43
- Receiver Statistics Vector 44
- Transmitting Outbound Frames 47
- Client Underrun 48
- Inter-Frame Gap Adjustment 49
- Transmitter Statistics Vector 50
- Using Flow Control 53
- Flow Control Basics 54
- Pause Control Frames 55
- Core-initiated Pause Request 56
- Pause Frame Reception Enabled 57
- Operation 59
- Chapter 6: Using Flow Control 60
- Chapter 7 61
- GMII Receiver Logic 63
- DCM Reset circuitry 64
- IOB LOGIC 66
- Virtex-4 Devices 67
- RGMII Receiver Logic 70
- Implementing External RGMII 71
- Using the MDIO interface 76
- Configuration and Status 77
- Configuration Registers 78
- Receiver Configuration 79
- Transmitter Configuration 80
- Flow Control Configuration 81
- MDIO Configuration 82
- Address Filter Configuration 82
- Accessing the Address Table 85
- LOCATION 86
- 31 : 0 47 : 32 86
- IDLE IDLE32 bits 87
- STA drives MDIO 87
- Constraining the Core 93
- MDIO Logic 94
- Flow Control 95
- Configuration 95
- "reset_dist_grp"; 96
- GMII Input Setup/Hold Timing 97
- Non-Virtex-5 devices 99
- RGMII IOB Constraints 101
- RGMII Input Setup/Hold Timing 102
- Virtex-5 Devices 103
- RGMII DDR Constraints 104
- Non-Virtex-5 Devices 105
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- Clocking and Resetting 109
- Multiple Cores 110
- With RGMII 111
- Reset Conditions 112
- Interfacing to Other Cores 113
- Tra ns ce i ve r 115
- Virtex-5 LXT and SXT Devices 117
- Virtex-5 FXT Devices 118
- Ethernet Statistics Core 119
- Implementing Your Design 123
- Implementation 124
- Static Timing Analysis 125
- Generating a Bitstream 125
- Generating a Simulation Model 125
- Using the Model 126
- Using the Client-Side FIFO 127
- Interfaces 128
- Receive FIFO 129
- Data Flow 130
- Functional Operation 131
- Expanding Maximum Frame Size 132
- Interoperability 133
- Appendix C 135
- Core Latency 137
- Appendix D: Core Latency 138
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