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UG144 April 24, 2009
Chapter 8: Configuration and Status
R
-- DISCONTINUED PRODUCT --
Read Transaction
Figure 8-7 shows a Read transaction; this is defined by OP=”10”. The addressed MMD
(PHYAD) device returns the 16-bit word from the register at REGAD.
For details of the register map of MMD (PHY layer devices) and a detailed description of
the operation of the MDIO Interface itself, see IEEE 802.3-2005.
Accessing MDIO With GEMAC
More information about MDIO with GEMAC can be found in the following sections of this
guide:
• For the GEMAC port definition of the MDIO, see “MDIO Interface” in Chapter 2
• “Connecting the MDIO to an Internally Integrated PHY,” on page 76
• “Connecting the MDIO to an External PHY,” on page 76
The management interface is also used to access the MDIO interface of the GEMAC core.
The MDIO interface supplies a clock to the connected PHY, mdc. This clock is derived from
the host_clk signal using the value in the Clock Divide[4:0] configuration register.
The frequency of mdc is given by the following equation:
The frequency of mdc given by this equation should not exceed 2.5 MHz to comply with
the IEEE 802.3-2005 specification for this interface. To prevent mdc from being out of
specification, the Clock Divide[4:0] value powers up at 00000. While this value is in
the register, it is impossible to enable the MDIO interface.
For details of the register map of PHY layer devices and a detailed description of the
operation of the MDIO interface itself, see IEEE 802.3-2005.
Figure 8-7: MDIO Read Transaction
Z1 1 1 0 1 0 P4 P3 P2 P1 P0 R4 R3 R2 R1 R0 Z 0 D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1 ZZZ
mdc
mdio
IDLE IDLE32 bits
PRE
ST OP PRTAD REGAD TA 16-bit READ DATA
STA drives MDIO MMD drives MDIO
f
MDC
f
HOST_CLK
1 Clock Divide[4:0]+()2×
--------------------------------------------------------------------=
- LogiCORE™ IP 1
- 1-Gigabit Ethernet 1
- MAC v8.5 1
- Revision History 3
- Table of Contents 5
- Appendix D: Core Latency 8
- Schedule of Figures 9
- UG144 April 24, 2009 10
- Schedule of Tables 13
- About This Guide 15
- Conventions 16
- Online Document 17
- List of Acronyms 17
- Introduction 19
- Specifications 20
- Technical Support 20
- Feedback 20
- Core Architecture 21
- Core Components 22
- Core Interfaces 23
- Client Side Interface 26
- Receiver Interface 27
- Flow Control Interface 27
- Physical Side Interface 29
- MDIO Interface 30
- Generating the Core 31
- Component Name 32
- Management Interface 32
- Address Filter 32
- Physical Interface 32
- Output Generation 33
- Designing with the Core 35
- Know the Degree of Difficulty 37
- Keep it Registered 38
- Use Supported Design Flows 38
- Chapter 5 39
- Frame Reception with Errors 41
- Client-Supplied FCS Passing 42
- VLAN Tagged Frames 42
- Disabled 43
- Receiver Statistics Vector 44
- Transmitting Outbound Frames 47
- Client Underrun 48
- Inter-Frame Gap Adjustment 49
- Transmitter Statistics Vector 50
- Using Flow Control 53
- Flow Control Basics 54
- Pause Control Frames 55
- Core-initiated Pause Request 56
- Pause Frame Reception Enabled 57
- Operation 59
- Chapter 6: Using Flow Control 60
- Chapter 7 61
- GMII Receiver Logic 63
- DCM Reset circuitry 64
- IOB LOGIC 66
- Virtex-4 Devices 67
- RGMII Receiver Logic 70
- Implementing External RGMII 71
- Using the MDIO interface 76
- Configuration and Status 77
- Configuration Registers 78
- Receiver Configuration 79
- Transmitter Configuration 80
- Flow Control Configuration 81
- MDIO Configuration 82
- Address Filter Configuration 82
- Accessing the Address Table 85
- LOCATION 86
- 31 : 0 47 : 32 86
- IDLE IDLE32 bits 87
- STA drives MDIO 87
- Constraining the Core 93
- MDIO Logic 94
- Flow Control 95
- Configuration 95
- "reset_dist_grp"; 96
- GMII Input Setup/Hold Timing 97
- Non-Virtex-5 devices 99
- RGMII IOB Constraints 101
- RGMII Input Setup/Hold Timing 102
- Virtex-5 Devices 103
- RGMII DDR Constraints 104
- Non-Virtex-5 Devices 105
- -- DISCONTINUED PRODUCT 108
- Clocking and Resetting 109
- Multiple Cores 110
- With RGMII 111
- Reset Conditions 112
- Interfacing to Other Cores 113
- Tra ns ce i ve r 115
- Virtex-5 LXT and SXT Devices 117
- Virtex-5 FXT Devices 118
- Ethernet Statistics Core 119
- Implementing Your Design 123
- Implementation 124
- Static Timing Analysis 125
- Generating a Bitstream 125
- Generating a Simulation Model 125
- Using the Model 126
- Using the Client-Side FIFO 127
- Interfaces 128
- Receive FIFO 129
- Data Flow 130
- Functional Operation 131
- Expanding Maximum Frame Size 132
- Interoperability 133
- Appendix C 135
- Core Latency 137
- Appendix D: Core Latency 138
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