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70 www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
Chapter 7: Using the Physical Side Interface
R
-- DISCONTINUED PRODUCT --
The logic required to forward the transmitter clock is also shown. It has matching logic to
the data and control signals to provide a known relationship between the signals. An
IODELAY component is used to phase-shift the rgmii_txc clock signal by 90 degrees
with respect to gtx_clk_bufg. This allows the rising edge of rgmii_txc to occur in the
center of the data valid window—which maximizes setup and hold times across the
interface, as specified in the RGMII v2.0 specification. The IODELAY component is used in
fixed delay mode, where the attribute ODELAY_VALUE determines the tap delay value. An
IDELAYCTRL primitive must be instantiated for this mode of operation. See the Virtex-5
User Guide for more information on the use of IDELAYCTRL and IODELAY components.
RGMII Receiver Logic
Spartan-3, Spartan-3E, Spartan-3A and Spartan-3A DSP Devices
Figure 7-7 shows using the physical receiver interface of the core to create an external
RGMII in a Spartan-3 device. The signal names and logic exactly match those delivered
with the example design when the RGMII is selected. If other families are used, equivalent
primitives and logic specific to that family is used in the example design.
Figure 7-7 also shows that the input receiver signals are registered in device IOBs on rising
and falling edges of gmii_rx_clk_bufg. The signals are then registered inside the FPGA
fabric, before a final register stage to synchronize signals to the rising edge clock. To
achieve the required setup and hold times across the interface, the DCM uses a phase-shift
to adjust the clock relative to the data. See Appendix C, “Calculating DCM Phase-
Shifting.”
DCM Reset circuitry
A DCM reset module, not illustrated in Figure 7-7, is also present and is instantiated in the
example design next to the DCM. Since this logic must be reliable whatever the
reset/locked status of the DCM, the module requires a reliable reference clock. In the
example design for RGMII, a transmitter clock source is therefore used for this receiver
DCM.
This reset circuitry will generate an appropriate reset pulse for the receiver DCM of
Figure 7-7 under the following conditions:
• The locked signal from the DCM is constantly monitored. Following a high to low
transition on this signal, indicating that the DCM has lost lock, a reset will be issued.
• A timeout counter is enabled when the DCM is in the loss of lock state. If, following
the timeout period, the DCM has not obtained lock, another DCM reset will be issued.
This timeout counter will time a > 1ms interval. This timeout functionality is required
for DCMs connected to Ethernet PHYs since the PHYs may source discontinuous
clocks under certain network conditions (for example, when no ethernet cable is
connected).
For Spartan-3 families, the reset pulse is transferred into the DCM input clock (rgmii_rxc
from Figure 7-7). Here it is extended to three DCM clock periods duration and routed to
the reset input of the DCM.
- LogiCORE™ IP 1
- 1-Gigabit Ethernet 1
- MAC v8.5 1
- Revision History 3
- Table of Contents 5
- Appendix D: Core Latency 8
- Schedule of Figures 9
- UG144 April 24, 2009 10
- Schedule of Tables 13
- About This Guide 15
- Conventions 16
- Online Document 17
- List of Acronyms 17
- Introduction 19
- Specifications 20
- Technical Support 20
- Feedback 20
- Core Architecture 21
- Core Components 22
- Core Interfaces 23
- Client Side Interface 26
- Receiver Interface 27
- Flow Control Interface 27
- Physical Side Interface 29
- MDIO Interface 30
- Generating the Core 31
- Component Name 32
- Management Interface 32
- Address Filter 32
- Physical Interface 32
- Output Generation 33
- Designing with the Core 35
- Know the Degree of Difficulty 37
- Keep it Registered 38
- Use Supported Design Flows 38
- Chapter 5 39
- Frame Reception with Errors 41
- Client-Supplied FCS Passing 42
- VLAN Tagged Frames 42
- Disabled 43
- Receiver Statistics Vector 44
- Transmitting Outbound Frames 47
- Client Underrun 48
- Inter-Frame Gap Adjustment 49
- Transmitter Statistics Vector 50
- Using Flow Control 53
- Flow Control Basics 54
- Pause Control Frames 55
- Core-initiated Pause Request 56
- Pause Frame Reception Enabled 57
- Operation 59
- Chapter 6: Using Flow Control 60
- Chapter 7 61
- GMII Receiver Logic 63
- DCM Reset circuitry 64
- IOB LOGIC 66
- Virtex-4 Devices 67
- RGMII Receiver Logic 70
- Implementing External RGMII 71
- Using the MDIO interface 76
- Configuration and Status 77
- Configuration Registers 78
- Receiver Configuration 79
- Transmitter Configuration 80
- Flow Control Configuration 81
- MDIO Configuration 82
- Address Filter Configuration 82
- Accessing the Address Table 85
- LOCATION 86
- 31 : 0 47 : 32 86
- IDLE IDLE32 bits 87
- STA drives MDIO 87
- Constraining the Core 93
- MDIO Logic 94
- Flow Control 95
- Configuration 95
- "reset_dist_grp"; 96
- GMII Input Setup/Hold Timing 97
- Non-Virtex-5 devices 99
- RGMII IOB Constraints 101
- RGMII Input Setup/Hold Timing 102
- Virtex-5 Devices 103
- RGMII DDR Constraints 104
- Non-Virtex-5 Devices 105
- -- DISCONTINUED PRODUCT 108
- Clocking and Resetting 109
- Multiple Cores 110
- With RGMII 111
- Reset Conditions 112
- Interfacing to Other Cores 113
- Tra ns ce i ve r 115
- Virtex-5 LXT and SXT Devices 117
- Virtex-5 FXT Devices 118
- Ethernet Statistics Core 119
- Implementing Your Design 123
- Implementation 124
- Static Timing Analysis 125
- Generating a Bitstream 125
- Generating a Simulation Model 125
- Using the Model 126
- Using the Client-Side FIFO 127
- Interfaces 128
- Receive FIFO 129
- Data Flow 130
- Functional Operation 131
- Expanding Maximum Frame Size 132
- Interoperability 133
- Appendix C 135
- Core Latency 137
- Appendix D: Core Latency 138
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